Field-Programmable Gate Arrays Engineer

RTL Design & FPGA Engineer for an opportunity in San Jose, CA - OnsiteThe ideal candidate should have proven expertise in Verilog-based synthesizable RTLdevelopment, register map implementation, and modular RTL design. Strong experience withStrong experience with FPGA clocking structures and deterministic reset schemes is required.Required experience includes:Proven Verilog expertise in synthesizable RTL, register map implementation, and modular design.Strong understanding of FPGA clocking structures and deterministic reset schemes.Experience with at least one of the following FPGA toolchains:Microchip LiberoAMD/Xilinx VivadoHands-on experience writing SDC/XDC timing constraints, including clock definitions, I/O delays, and timing exceptions.Experience with FPGA I/O pin planning and device bank rules.Experience developing Makefile and/or Tcl-based build automation.Experience with Verilog and/or SystemVerilog simulation using tools such as VCS, Questa/ModelSim, or Vivado Simulator.Experience with embedded FPGA debug tools such as ILA, SignalTap, or ChipScope.Hands-on experience with lab board bring-up, PLD programming, and hardware debugging.Working experience with some standard protocols, such as AXI4/AXI-Lite, AHB-Lite, APB, PCIe, I2C, SPI, MDIO, or UART. Experience with all listed protocols is not required.Experience with Quartus or Lattice toolchains would be a plus.