Verification Engineer

Overview In this role you will lead and contribute to the verification of Network-on-Chip IPs and subsystems at AMD. You’ll architect and implement verification environments using SystemVerilog, UVM, and formal methods to prove functional correctness of NOC designs. You will collaborate with architects and design engineers to create thorough test plans, drive verification closure, and improve coverage. This position offers the opportunity to shape complex ASIC/SoC verification at scale within a world‑leading GPU/compute company. You’ll work in a hybrid setup, contributing to high‑impact projects that advance AMD’s next‑generation technology. ResponsibilitiesLead verification planning for complex digital blocks by interpreting architectures and specsCollaborate with architects and design engineers to craft a comprehensive verification planDesign and architect SystemVerilog/UVM testbenches to verify designs efficientlyBuild and enhance constrained-random, directed, and formal verification environments (SVA) and toolsDebug tests with engineers to ensure functionally correct blocksDevelop coverage measures and perform coverage analysis to close verification gaps Key requirementsProficient in SystemVerilog, UVM, and ASIC/SoC verification methodologiesExperience validating complex digital designs, ideally NoC architecturesConstraint-random, coverage-driven, and formal verification experience (SVA)Familiarity with gate-level simulation and debugging in large-scale projectsExperience with block-level or full‑chip verification for SOCs/FPGAKnowledge of verification tools and environments (e.g., VCS, IES) and assertion/coverage techniquesBachelor's or Master's in Computer Engineering or Electrical Engineeringanalyticaldetail-orientedcollaborativeSystemVerilogUVM/OVM/VMMSystemVerilog Assertions (SVA)