Silicon Design Package Engineer

Silicon Design Package EngineerLocation: Santa Clara, CAThis role is highly specialized in semiconductor packaging design, requiring strong EDA tool proficiency and knowledge of advanced packaging technologiesTools & Knowledge:Mentor/Siemens and Cadence tools (especially for Package Layout Automation - PLA).Technical Expertise:Multi-layer package design experience.Understanding of substrate manufacturing Design Rules and Assembly Rules.Familiarity with SIPI (Signal Integrity & Power Integrity) Rules.