DFT Engineer

Job Title: DFT Engineer (Design for Test) – SemiconductorLocation: Austin, TX (On-site) Experience: 10–15 YearsRole OverviewWe are looking for an experienced DFT Engineer to drive end-to-end Design-for-Test (DFT) architecture and implementation for complex digital and mixed-signal SoCs. This role involves close collaboration with design, verification, and backend teams to ensure high-quality, testable silicon.Key ResponsibilitiesDefine and implement SoC-level DFT architecture (ATPG, Scan, MBIST, LBIST)Insert and integrate DFT structures: scan chains, boundary scan, compression, TAP, clock control, etc.Execute hierarchical DFT design and integrationDebug DFT DRC issues and improve test coverage/qualityDevelop and validate silicon test strategies (post-silicon bring-up, ATE debug)Work on MBIST implementation and memory test integrationSupport test planning for analog/mixed-signal IPsDocument DFT methodologies and processesRequired Skills & ExperienceStrong experience in DFT architecture, insertion, and validationHands-on experience with silicon bring-up, ATE debug, ATPG (including compressed patterns), MBIST, and JTAGSolid understanding of fault modeling and test coverageExperience in IP integration (memories, TAP controllers, MBIST, test controllers)Proficiency in EDA tools such as DFT Compiler/Fusion Compiler, Tessent, Modus, SpyGlass, TestKompressStrong understanding of ASIC design flow (synthesis, simulation, verification)Additional RequirementsMust have recent hands-on experience in DFTStrong stability in career (no frequent job changes or gaps)Willingness to work on-site in Austin, TX (5 days/week)