RTL Verification Engineer - Memory & Cache Systems

Apple Inc. in Austin, Texas is seeking an experienced RTL verification engineer to validate design functionality, implement testbenches with SystemVerilog and UVM, and ensure compliance with architectural specs. You will run and debug simulations, generate coverage analyses, and refine testbenches for reusable, scalable verification workflows across SRAMs, register files, and caches. Collaboration with circuit teams and use of industry tools are essential.#J-18808-Ljbffr