Full Stack Engineer

ME/BE with a minimum of 8-15 years of experience. Hands-on knowledge of SystemVerilog and Verilog is mandatory. Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments. Proven expertise in designing and optimizing scheduling and QoS mechanisms. Experience with Ethernet and IP protocols. Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues. Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.