Power Optimization Engineer

Hi,We are hiring for our client, Please let me know if you are interested!Title: Power Optimisation EngineerLocation: Can work at any client location in the USA.Work Type : Full Time Direct HirePay Range : $200k - $205k with benefitsUS Citizenship or Green Card RequiredPosition Summary:We are seeking a highly motivated Power Analysis / Power Optimization Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for comprehensive power analysis, optimization, and methodology development across the RTL-to-GDSII design flow. This role requires expertise in Synopsys power tools, low-power design techniques, and automation scripting to improve design efficiency and power-performance-area (PPA).Key Responsibilities • Perform comprehensive power analysis in vector-based and vector-less modes across ASIC/SoC design stages from RTL to gate-level netlists.• Develop, enhance, and automate power analysis flows and methodologies.• Investigate power inefficiencies and provide optimization recommendations to design teams.• Present power analysis findings and recommendations to cross-functional engineering teams.• Collaborate with Physical Design teams on clock tree synthesis (CTS), floorplanning, and implementation optimizations.• Support memory power optimization through memory selection and traffic analysis.• Execute synthesis and physical design experiments to identify optimal PPA solutions.• Drive low-power implementation and signoff activities using industry-standard methodologiesRequired Skills & Qualifications: • 3–6+ years of experience with PrimePower, PrimeTime PX (PTPX), PowerArtist, or Cadence Voltus. • Strong understanding of Synopsys power flows (PrimePower and PTPX). • Experience with RTL-to-GDSII design flows in advanced technology nodes (7nm and below).• Knowledge of low-power implementation techniques including clock gating, power gating, multiple voltage domains, UPF, and CPF.• Understanding of netlists, UPF, SPEF, and power signoff methodologies.• Familiarity with physical design concepts including floorplanning, CTS, and PnR flows.• Working knowledge of Synopsys Fusion Compiler and synthesis/PnR flows.• Strong TCL scripting skills (mandatory).• Proficiency in Python scripting for flow automation (preferred).• Knowledge of NoC and clocking architecture power optimization.• Strong written and verbal communication skills.Preferred Qualifications:• Experience with RTL power optimization using PowerArtist.• Familiarity with memory architectures including SRAM, DRAM, register files, and FIFO structures.• Knowledge of library characterization tools and analysis.• Experience analyzing FSDB waveforms for design profiling and power reduction.• Exposure to version control systems and automation frameworks.