Test Engineer

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolutionEfficient Computer is a fabless semiconductor startup headquartered in Pittsburgh, PA, building energy-efficient processors for edge compute, embedded AI, and high-performance applications. Our team designs, tapes out, and brings up custom silicon across multiple process nodes, working closely with world-class foundry and OSAT partners to deliver differentiated chips from concept to production. Efficient Computer is looking for a Test Engineer with hands-on DFT and fabless semiconductor test experience to join our Operations team. This is a mid-level role sitting at the intersection of Hardware Engineering and Supply Chain and Operations.The right candidate has worked across the full test lifecycle - from DFT strategy and ATPG pattern generation through ATE bringup, OSAT coordination, and production test - and is equally comfortable working with external suppliers as they are with internal hardware engineers. You will serve as the primary interface between our engineering team and our foundry, OSAT, and test partners, owning test engineering across our active chip programs and scaling that foundation to future products.What You Will DoDFT Strategy and Pattern DevelopmentPartner with external design partners and internal hardware engineers to define and execute DFT strategy for each chip programGenerate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory read and write sequencesDevelop and maintain STIL and PDL test program files for ATE executionDrive DFT sign-off deliverables and resolve pattern-level issues in coordination with external partnersSupport setup pattern generation including power-up and power-down sequences, DFT entry sequences, and test mode initializationUnderstand and define power rail sequencing requirements for ATE execution to ensure safe device bringupATE Bringup and Test Program DevelopmentDevelop and debug test programs on ATE platforms including Advantest and Teradyne systemsExecute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teamsCharacterize device behavior across voltage, temperature, and frequency cornersSupport load board bring-up and interface hardware validationDefine and manage test flows including wafer probe, final test, and bin sortUnderstand test time optimization strategies such as pattern flow sequencing to minimize unnecessary power cyclesOSAT and Supplier CoordinationServe as the primary test engineering interface with OSAT partners and test housesManage test program handoff to OSAT including documentation, qualification, and acceptance criteriaCoordinate pattern delivery between design partners and OSAT to ensure format compatibility across STIL and SVF as requiredTrack and analyze yield data from probe and final test, escalate anomalies, and drive corrective actionsSupport die traceability and OTP programming flows in production bin sortCoordinate with supply chain and operations on test capacity planning and lot schedulingCross-Program OwnershipOwn test engineering across multiple active chip programs simultaneouslyBuild scalable test infrastructure and documentation that carries forward to future programsContribute to DFT reviews, tapeout checklists, and test escape analysisHelp define and mature internal test engineering capabilities over timeRequiredWhat You Bring5+ years of semiconductor test engineering experience in a fabless or IDM environmentHands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG boundary scanExperience generating and validating STIL patterns and working with test pattern delivery packagesATE test program development experience on Advantest or Teradyne platformsExperience supporting wafer probe and final test at an OSAT or test house, including load board bringupFamiliarity with power sequencing requirements and DFT entry flows for ATE test program developmentAbility to work directly with external design partners and OSAT suppliers to coordinate pattern delivery and test executionStrong written and verbal communication skills - this role requires ongoing collaboration with external partners across multiple time zonesPreferredExperience with embedded memory test including characterization and programming of non-volatile memory technologiesExposure to high-speed serial interface test such as memory interfaces or camera and display interconnect protocolsFamiliarity with DFT tools from major EDA vendorsExperience at a fabless startup or small team where test engineering scope is broadExposure to leading-edge process nodes at 28nm or belowExperience with ATE yield analysis and test time optimizationScripting ability in Python or Perl for data analysis and test automationExperience generating VCD from RTL simulation and porting to STIL formatWe offer a competitive salary for this role, generally ranging from $150,000 to $190,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.Why Join Efficient?Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.