Memory Layout Engineer - DRAM, Automation & Verification

Micron Technology, Inc is seeking a motivated individual to contribute to the development of new memory products in Boise, Idaho. As part of the team, you will assist with the layout and optimization of memory circuits, ensuring adherence to quality standards through verification checks and debugging. Ideal candidates will hold a relevant Bachelor's degree and possess skills in Cadence and Calibre tools. The position offers exceptional benefits including healthcare plans, paid time off, and opportunities for professional growth. J-18808-Ljbffr