Senior Technical Lead - Silicon Platform Validation, Python

Senior Technical Lead - Silicon Platform Validation, PythonSanta Clara, CaliforniaWe are seeking an Emulation Build Engineer to own the end-to-end process of building, compiling, and validating RTL design models targeting hardware emulation and prototyping platforms — specifically Cadence Palladium, Cadence Protium, and/or Synopsys ZeBu. You will be the critical bridge between RTL design teams and validation/software teams, ensuring that high-quality, synthesizable emulation models are delivered on schedule to enable early firmware development, hardware-software co-verification, and system-level validation.Key ResponsibilitiesEmulation Model Build & CompilationBuild, compile, and optimize RTL-to-gate/behavioral models targeting Palladium, Protium, and/or ZeBu emulation platformsOwn the emulation build flow from RTL ingestion through synthesis, partitioning, mapping, place-and-route, and bitstream/image generationResolve synthesis and compilation errors including unresolved modules, black-box instantiation, clock/reset inference, memory mapping, and multi-driver conflictsImplement and maintain RTL waivers, workarounds, and design abstraction (memory wrappers, analog stubs, IP replacements) to achieve clean compilationsOptimize build configurations for compile time, resource utilization, emulation speed (MHz), and capacity across target platformsManage incremental and hierarchical build strategies to reduce turnaround time for design iterationsSupport multi-domain and multi-clock designs with proper clock modeling and domain crossing handlingModel Validation & QualityValidate emulation models through sanity tests, boot tests, and golden-reference comparisons against RTL simulationEnsure functional equivalence between RTL simulation and emulation by running correlation test suitesDebug and resolve model mismatches (simulation vs. emulation) due to synthesis artifacts, X-state handling, timing differences, or initialization issuesValidate memory models, I/O interfaces, and transactor/synthesizable BFM integrationPerform coverage analysis on emulation models and track model quality metricsMaintain a regression suite for build-level validation (smoke tests, connectivity checks)Infrastructure & AutomationDevelop and maintain automated build pipelines (CI/CD) for nightly/weekly emulation model buildsCreate scripts and tools for build monitoring, error triage, capacity tracking, and build status reportingMaintain version-controlled build configurations, design collateral, and release notesManage compute farm resources (LSF/SGE/Slurm) and optimize job scheduling for emulation buildsTrack and manage platform licenses and capacity allocation across projectsDevelop dashboards and metrics for build health, turnaround time, and platform utilizationCollaboration & SupportPartner with RTL design teams on design readiness, coding guidelines, and synthesizability best practices for emulationWork with verification/validation teams to integrate transactors, probes, and debug infrastructure into emulation modelsCollaborate with firmware/software teams to deliver validated models for early SW development and hardware-software co-validationSupport silicon bring-up teams with emulation-correlated debug and pre-silicon regression dataParticipate in project planning to communicate build schedules, risks, and dependenciesSkill RequirementsEducation: B.S./M.S. in Electrical Engineering, Computer Engineering, or related fieldExperience: 3–8+ years in emulation model build, FPGA prototyping, or related hardware compilation rolesHands-on experience with one or more emulation/prototyping platforms:Platform Key Skills Cadence Palladium xeCompiler, xeDesignOptimizer, multi-domainStrong understanding of RTL design constructs and synthesizability rules (Verilog/SystemVerilog)Experience with logic synthesis concepts (technology mapping, optimization, timing constraints)Proficiency in scripting and automation: Python, Perl, Tcl, Bash, MakefilesKnowledge of memory modeling (SRAM, ROM, FIFO wrappers) and abstraction for emulationFamiliarity with clock modeling strategies (clock generators, clock muxes, PLLs) in emulationUnderstanding of design hierarchy, IP integration, and SoC-level build complexityExperience with version control (Git, Perforce) and build management systemsOther Requirements:Platform Key Skills Cadence Palladium xeCompiler, xeDesignOptimizer, multi-domain clocking, ICE/SCE modes, speed optimizationCadence Protium FPGA-based prototyping, partitioning, multi-FPGA mapping, pin multiplexing, timing closureSynopsys ZeBu zFAST/zTOP compile, design partitioning, ZCUI, transactor integration, ZeBu ServerCompensation and BenefitsA candidate's pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year.