Sr Hardware Design Engineer - PCIe Interface - Hybrid (Santa Clara)

Founded in 2016 and headquartered in the San Francisco Bay Area, we are building the worlds fastest AI supercomputer meaning the smallest, fastest and greenest general-purpose chip with wide applications in hyperscale data centers, private cloud, and AI/high-performance computing.We are actively interviewing for a Sr Hardware Design Engineer who has experience implementing, debugging, and verifying a high-performance PCIe interface including helping build the infrastructure to support PCIe during FPGA emulation and bringup.Top Reasons to Work with UsJoin a well funded startup having an immediate impact day 1!Competitive Base + EquityMedical, Dental, Vision, 401KPTO, Holidays, Remote Work, and more!What You Will Be DoingWorking with a small team to implement, debug, and verify a high-performance PCIe interfaceBuild the infrastructure to support PCIe during FPGA emulation and bringupWhat You Need for this PositionBS in related field10+ years of experiencePCIe controller/device designBus traffic analyzers and logic analyzersData eye and BER analysisVerilog / System Verilog / Synthesis / STA / CDC / Lint experienceSo if you are a Sr Hardware Design Engineer w/ PCIe Interface experience, please apply today!