Senior FPGA Prototyping Engineer

We are seeking a High-Caliber FPGA Prototyping Engineer to lead the pre-silicon validation of next-generation SmartNIC . Mountain View, CA (Hybrid) 12-18 month contract FTE with Prodapt - Benefits/PTO/401k options Key Responsibilities HAPS Prototyping: Lead the end-to-end prototyping process using Synopsys HAPS-100/HAPS-80 platforms Multi-FPGA Partitioning: Execute complex design partitioning across multiple FPGAs using ProtoCompiler , ensuring high-performance system-level functional accuracy. Protocol Validation: Drive deep-dive validation of high-speed signaling interfaces, including PCIe Gen 5/6 and 100G/400G Ethernet . Hybrid Emulation: Collaborate on hardware-software co-design by integrating HAPS rigs with virtual environments (Zebu or C-Models) to jumpstart software validation. Deep-Dive Debugging: Use logic analyzers, SynplifyPro , and SystemVerilog to isolate and resolve complex RTL bugs within the hardware prototype. Qualifications Experience: 7 to 12+ years in FPGA Prototyping and ASIC Validation. HAPS Expertise: Demonstrated mastery of the Synopsys HAPS ecosystem and ProtoCompiler toolchain is a mandatory requirement. Networking Fundamentals: Strong knowledge of SmartNIC architectures, network acceleration, or offload engines. Timing Closure: Proven track record of achieving high-speed timing closure on large-scale, multi-FPGA systems. J-18808-Ljbffr