FPGA Engineer
FPGA Verification EngineerUST is seeking an experienced FPGA Verification Engineer to work onsite in Mountain View, CA. The role focuses on verification of complex FPGA designs using SystemVerilog and UVM, ensuring functionality, performance, and reliability. The engineer will collaborate closely with FPGA design teams and contribute to verification strategy and execution.
Key Responsibilities:
- Develop and maintain verification testbenches using SystemVerilog, UVM, and RTLWrite, execute, and debug test cases covering functionality, performance, and corner cases
- Perform code and functional coverage analysis
- Identify, debug, and resolve design issues in collaboration with design engineers
- Participate in design and verification reviews
- Contribute to overall verification strategy and best practices
- Stay current with verification methodologies and industry tools
- Mandatory SkillsStrong understanding of FPGA design principles and architectures
- Hands-on experience with FPGA verification
- Proficiency in SystemVerilog and UVMExperience with verification tools such as QuestaSim, Synopsys VCSStrong debugging and problem-solving skills
- Excellent communication and collaboration skills
Required Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in FPGA design and/or verification
- Familiarity with Verilog and VHDLExperience working in Linux environments
- Good-to-Have / Desired Skills
- Experience with Python or Perl scripting
- Knowledge of high-speed interfaces and protocols (PCIe, I2C, SPI)
- Hands-on experience with lab debugging tools (Logic Analyzer, Oscilloscope, JTAG)