Performance Modeling Architect - AI Memory Systems

Job Title: Performance Modeling Architect - AI Memory SystemsJob Location: Santa Clara, CA, or Boston, MACompensation: $200K - $250K base DOE plus 25% bonus and meaningful equityRequirements: AI Memory Systems, Performance Modeling, Memory Expansion (NICs, SmartNICs, CXL, IPU/DPU, NoC), Memory Systems Architecture, ML Systems, CUDA Memory ManagementPosition OverviewWe are seeking a Member of Technical Staff, Performance Modeling to develop performance models for our fabric-attached memory expansion device for AI accelerators.You'll work closely with silicon architects and workload teams to explore design tradeoffs, validate performance assumptions, and identify bottlenecks early in the development cycle. This role is well-suited for engineers who enjoy reasoning from first principles, working with incomplete information, and co-exploring the design space as hardware and software evolve together.Key ResponsibilitiesBuild and maintain system-level performance models for a high-bandwidth data movement device operating in the scale-up domain.Model workload from software memory access patterns to data distribution in the network and all the way down to on-device memory channels.Work day-to-day with silicon architects, system designers, and workload owners to align performance expectations and constraints.Identify performance bottlenecks, scaling limits, and sensitivity points across compute, memory, and interconnects in end-to-end workload settings.Clearly communicate modeling assumptions, limitations, and conclusions to both technical and non-specialist stakeholders.QualificationsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field.Ability to quickly learn new ML architectures as soon as they come out, and build performance models for them.5-10+ years of experience in performance modeling for data movement devices: NICs, memory expansion cards (e.g., CXL), IPU/DPU, NoC.Ability to reason across multiple abstraction layers, from architectural details to system-level performance behavior.PreferredQualificationsPhD in Computer Science, Electrical Engineering, or a related field.Prior experience modeling performance for networking protocols with memory semantics.Understanding of ML systems: workload sharding, KV caching hierarchies, attention optimizations, trade-offs when deploying ML models at scale, and various assumptions.Familiarity with shared memory systems and frameworks (e.g., CUDA VMM).Experience with scale-up and high-bandwidth interconnects (e.g., NVLink or similar technologies).BenefitsCompetitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grantComprehensive benefits including health, dental, vision, and life insuranceWell-equipped, sunny offices in Santa Clara, CA and Boston, MARelocation assistance and visa sponsorshipPerks include a daily lunch stipend, 401k match, and moreA collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing