Engineer, Senior|5288 Engineer, Senior|5288

Job Description: Job Description : Join our Technologies Inc Global CAD team delivering SoC design CAD Tools for leading-edge products. The position requires experienced CAD development Engineer to develop RTL2GDS implementation tools and flows for new methodologies of PPA and Sign-off in cutting edge process nodes.CAD team at QCOM is looking for long term Temp staffing for driving Tools and Flows for upcoming Snapdragon products. These are key words for role and responsibility: Synthesis, Floorplan, Place and Route, Static Timing analysis, IR drop analysis, Physical verification and Logic verification. The Tools and flows are based on EDA vendors Synopsys, Cadence, Mentor, Ansys who deliver EDA tools for Chip design. Keywords tools and vendors Synopsys : Fusion Compiler, Design compiler (DC), Formality, Tetramax, PrimeTime, STAR-RC, IC validator Cadence : Genus, Innovus, Conformal, Tempus, Voltus Mentor : Aprisa, AtopTech, Tessent, Calibre Ansys: redhawk, Totem These engineers may have worked at these vendors, or at chip companies. If they have worked at ANY EDA vendor, that is a BIG PLUS At chip companies, engineers titles will be CAD engineer, PD engineer, Synthesis engineer. They are NOT CAD engineers but they can still be trained by CAD team, depending upon their interest in LEARNING the deep-down knowledge of tools and not just push buttons. This is a very high value skill which CAD engineers build. We also have work in adjacent areas. If a candidate has done Spice simulations, IP design, memory design we can check them as well. For CAD, it is good idea to have some automation skills. Tcl, PERL, Python are good languages to know and help. Overall our team builds tools and flow for the most complex chips, in most advanced technologies. We welcome the engineers to learn and build latest tool platforms.This roles responsibilities will include:Develop and support CAD tools and flows for Synthesis, Floorplan, Place and Route and ECODebug issues and provide solutions for design closure in advanced process nodsRegression, Test, analysis of QoR results and develop recipe for PPA and runtime/compute optimizationCollaboration with design teams, CAD teamsInterfacing with EDA vendors to enable production-ready tool sets that satisfy projects requirementMinimum Qualification Requirements:Hands on expertise in developing and maintaining CAD tool for digital designKnowledge of Industry EDA tools and PPA optimization techniquesStrong logical and creative problem-solving skills with excellent analytical and debugging skillsExcellent interpersonal and analytical skills with the ability to work independentlyHighly motivated, excellent team spirit, product and customer oriented4-8 years experiencePreferred Qualifications3+ years CAD flow development for ASIC design, floorplan, place and route and related work experience2 + year of experience in advanced process technology.2+ years experience with EDA vendor tools.2+ years hands-on experience with Tcl and Python languagesEducation QualificationsRequired: Bachelors Computer Engineering and/or Computer Science and/or Electrical Engineering with courses on VLSI and/or CAD toolsKey Words: Synopsys IC Compiler, ICC2, Encounter, Innovus, StarRC, Prime Time, Mentor Graphics Calibre, ICV, Formality, Design Compiler, TCAD, Cadence Virtuoso, Apache RedHawk.Comments for Suppliers: 3/21/2022: This is a clone of previous req. 5010012-1 - Please do not submit candidates who were previously disqualified.3/21: Urgent fill for 2 seats3/21: 100% Remote