ASIC/SoC Design Engineer, RTL design for SoC IPs

WHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The RoleJoin AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.The PersonThe ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle—from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.Key ResponsibilitiesRTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.SOC Integration: Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry-standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.Physical Design Collaboration: Work closely with physical design engineers on floor planning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.Cross-Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges and deliver high-quality silicon on schedule.Required QualificationsProven track record with 2+ production ASIC tape-outs in senior design rolesExpert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practicesHands-on experience with the complete ASIC design flow: RTL → Synthesis → STA → Physical Design → Tape-outExperience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraintsExperience integrating complex IP blocks into SOC designsKnowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)Bachelor's or Master's degree in Electrical Engineering or Computer EngineeringPreferred QualificationsKnowledge of ARM architecture and AMBA protocol specificationsFamiliarity with PCIe or CXL transaction layer protocolsExperience with low-power design techniques (clock gating, power gating, voltage scaling)Proficiency in scripting languages: Python, Perl, Tcl, or Shell scriptingExposure to formal verification tools for equivalence checking and property verificationFamiliarity with AI-assisted design tools and modern EDA technologiesExperience mentoring junior engineers and leading design teamsStrong technical writing skills for design specifications and documentationExcellent communication and collaboration skills in cross-functional environmentsLOCATION: San Jose, CAThis role is not eligible for visa sponsorship.Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.