Design Verification Engineer

Design Verification Services: Comprehensive verification of designs using advanced methodologies.Testbench Development: Creation of testbenches using System Verilog Universal Methodology (UVM), Python, and C, tailored for various testing scenarios.C Tests/API Integration: Development and integration of C tests, APIs, and software build flows to ensure robust testing.UVM Testbench Integration: Seamless integration of UVM testbenches for efficient testing processes.Test Development and Debugging: Developing and debugging tests for functionality, power, performance, error handling, and connectivity, applicable to both RTL and Gate Level Netlist designs.Continuous Integration & Regression Testing: Setup and debugging of continuous integration and regression testing for simulations at RTL and Gate Level Netlist.Power-Aware Simulation: Utilization of Unified Power Format (UPF) for power-aware simulation and emulation.XProp Simulation/TestBench Maintenance: Creation and maintenance of XProp simulations and testbenches.Coverage and Documentation: Collection and closure of coverage, along with thorough documentation of tests, testbenches, use cases, exclusions, and status updates.