Chip Packaging Design Engineer

· 5+ years’ experience completing layouts of high pin count, multi-layer organic build-up packages using Cadence APD and SiP package design tools. · Creating die and BGA symbols from scratch or from spreadsheet inputs · Setting up design environment, including tech files, stack ups, and constraints · Setting up Constraint Manager from scratch for complex packages (diff pair creation, multiple power supplies, net and zone specific constraints. · Routing signals and matching length both manually and using tool features · Design file management and documentation from initiation to final signoff · Generation of POD · Solid knowledge of top package suppliers design rules and basic manufacturing practices Job Type: Full-time Pay: $59,288.21 - $153,964.46 per year Schedule: 8 hour shift Day shift Ability to commute/relocate: Mountain View, CA 94035: Reliably commute or planning to relocate before starting work (Required) Work Location: In person