Interface Design Verification Engineer

Job Title: Interface Design Verification EngineerLocation: San Jose, CAEmployment Type: Contract / Full-TimeDuration: Contract duration to be confirmedFull-Time Salary: $170,000/yearFull-Time: Benefits to be confirmed with POC.Job Summary:Looking for an Interface Design Verification Engineer with strong SystemVerilog, UVM, and protocol verification experience. The engineer will verify interface IPs such as PCIe, DDR, Ethernet, and USB.Responsibilities:Verify interface IPs for protocol compliance.Develop UVM testbenches using VIPs.Perform corner-case and stress testing.Debug protocol-level failures.Work with design teams to ensure specification compliance.Required QualificationsStrong SystemVerilog and UVM experience.Experience with PCIe, DDR, Ethernet, USB, or similar protocols.VIP integration experience.Protocol compliance verification experience.Protocol debugging experience.ASIC, SoC, or Interface IP verification experience.3–8+ years of relevant Design Verification experience preferred.BS/MS in EE, ECE, CE, or related field preferred.Work Requirements:Ability to work in San Jose, CA as required.High-speed interface experience preferred.Protocol analyzer experience preferred.PHY-layer or SerDes knowledge preferred.Equal Opportunity Employer:We provide equal employment opportunities to qualified applicants in accordance with applicable federal, state, and local laws.Application: Interested candidates may submit an updated resume highlighting SystemVerilog, UVM, PCIe/DDR/Ethernet/USB, VIP integration, and protocol verification experience.