Senior Silicon Development Engineer DFT & Bring-Up

AMD in San Jose, CA is seeking a DFT engineer to implement and verify DFT architectures and features. You will perform scan insertion, ATPG pattern generation, and gate-level ATPG verification, contributing to post-silicon yield learning. The candidate should have hands-on experience with DFT methodologies, Mentor Testkompress or Synopsys Tetramax/DFTMAX, and Verilog RTL design, with strong problem-solving and communication skills. #J-18808-Ljbffr