Sr Design Verification Engineer - RISC-V & CPU
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Design Verification Engineer - Senior Level (15+ years)Duration: 10-12+ Months ContractLocations: Remote (California, oregon, Washington)Pay Range: $80-$85/hr on W2, 40 HrsDescription:The top 6 are must skills and rest are preferred skills, and of course it goes without saying that basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc.1)RISC-V architecture knowledge and verification experience2)VC Formal DPV App (Datapath Verification) which checks the RTL against C/C++ models for arithmetic conformance3)L3 cache coherent system with AXI and CHI interfaces4)C/C++5)Synopsys tools, VCS, VC Formal6)Python based simulation flow7)Wide Vector Unit and a Matmul Unit.8)Formal verification9)SOC System integration is also required, like booting Linux OS10)GLS (Gate Level Simulation)11)Low Power experience (CPF/UPF)