Head of Performance Visibility

About EtchedEtched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.Job SummaryWe are hiring a Head of Performance Visibility to define how performance is understood across next-generation AI accelerator systems.Our ML accelerator platform spans custom silicon, supercomputing software, compiler stacks, runtime libraries, and distributed inference environments. Performance at this scale is no longer a device-level question - it is a high-performance distributed system problem. You will define the performance metrics that connect raw hardware signals to distributed workload context, ML cluster dynamics, pod communication patterns, and emergent bottlenecks.This role requires more than telemetry. You will establish new abstractions, structured counter ontologies, cross-layer event correlation frameworks, distributed time-alignment strategies, and scalable reasoning systems operating across nodes, racks, and clusters. Working at the intersection of hardware design, driver architecture, runtime systems, and ML infrastructure, you will shape how these layers expose and consume performance intelligence. This is a foundational role defining not just tooling, but how our platform reasons about efficiency, scalability, and system behavior for years to come.Key Responsibilities besides Mentorship and LeadershipSystem-Level Performance DesignDefine the architectural approach for collecting and structuring telemetry across CPUs, drivers, interconnects, and multiple acceleratorsDesign scalable models for correlating performance events across device and host boundariesCross-Layer Event CorrelationDevelop mechanisms to align hardware counters, runtime activity, communication phases, and workload semantics across model-layer execution into coherent, actionable insightImplement time synchronization and trace-alignment strategies across multi-device systemsTelemetry & Counter ModelingDefine structured counter taxonomies separating base signals from derived metricsDesign derived performance models bridging low-level hardware signals and workload-level behaviorInfluence instrumentation strategy for future hardware generationsDistributed Performance ReasoningBuild tools that identify bottlenecks among multi-accelerator workloads across chips within hostsBuild cluster-scale performance analysis for distributed inference across data center networksTooling & Insight DeliveryContribute to analysis engines and developer-facing tooling that transform raw telemetry into intuitive insightShape how performance intelligence is surfaced to engineers debugging large-scale AI systemsYou may be a good fit if you haveDeep experience building complex systems at the intersection of hardware and softwarePersonally envisioned and built significant portions of profiling, tracing, or observability systems - not solely defined requirements or product strategyDemonstrated ability to translate raw hardware signals into scalable, production-grade telemetry and analysis infrastructureExperience correlating time-series events across distributed systemsDeep systems programming expertise (C++ or Rust), with a track record of shipping low-level infrastructure operating close to hardware or runtime systemsExperience designing distributed correlation mechanisms, timestamp-alignment strategies, or performance modeling frameworks across multiple devices or hostsExperience designing distributed tracing or observability platforms at scaleExperience with high-performance computing systems and large AI training clustersExperience with timestamp synchronization strategies and event alignment in distributed environmentsExperience with hardware counter design and instrumentation strategyExperience with performance modeling for large-scale ML workloadsExperience leading cross-functional architectural initiatives spanning hardware and software teamsBenefitsMedical, dental, and vision packages with generous premium coverage$500 per month credit for waiving medical benefitsHousing subsidy of $2k per month for those living within walking distance of the officeRelocation support for those moving to San Jose (Santana Row)Various wellness benefits covering fitness, mental health, and moreDaily lunch and dinner in our officeHow we're differentEtched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.