Senior Lead Engineer - PD

Job RequirementsWho We Are:Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skillsAbout The RoleWe are looking for a Physical Design Engineer with expertise in 3D SoC / advanced packaging technologies to drive the implementation of complex multi-die silicon systems.You will work closely with architecture, RTL, packaging, and signoff teams to deliver high-performance, power-efficient, and manufacturable silicon solutions using advanced 2.5D/3D integration technologies.ResponsibilitiesOwn physical implementation of complex blocks or subsystems in advanced technology nodes (5nm / 3nm and beyond).Drive floorplanning, placement, CTS, routing, and timing closure for large SoC blocks.Implement and optimize designs for 3D IC / 2.5D integration (chiplets, stacked die, interposers).Work with packaging and architecture teams to define die partitioning, TSV placement, micro-bump planning, and interconnect strategies.Perform power, timing, signal integrity, and IR drop analysis across multi-die systems.Drive PPA (Power, Performance, Area) optimization for high-performance compute workloads.Collaborate with DFT, RTL, packaging, and sign-off teams to ensure design convergence and tape-out readiness.Develop and improve automation scripts and flows for large-scale physical implementation.Support post-silicon analysis and debug when required.Minimum QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.5+ years of experience in physical design and implementation of advanced SoCs.Strong hands-on experience with full physical design flow:FloorplanningPlacementClock Tree Synthesis (CTS)RoutingTiming closurePhysical verificationExperience with EDA tools such as:Synopsys ICC2 / Fusion CompilerCadence InnovusPrimeTime / TempusExperience with advanced process nodes (≤7nm).Strong scripting skills in TCL / Python / Perl.Work ExperiencePreferred QualificationsExperience with 3D IC technologies, including:TSV (Through-Silicon Via) integrationMicro-bump interconnectsDie-to-die interfacesChiplet architecturesFamiliarity with 2.5D/3D packaging technologies (CoWoS, EMIB, hybrid bonding).Knowledge of power delivery networks across stacked dies.Experience with thermal analysis in 3D ICs.Exposure to high-performance compute, AI accelerators, or data center SoCs.Experience working on full chip or multi-die tape-outs.Key SkillsAdvanced Physical Design Implementation3D IC / Chiplet ArchitectureTiming Closure & SignoffPower Integrity / Signal IntegrityEDA Flow Development & AutomationCross-team silicon development collaborationBenefitsPay Range : $150K - $180KWork RequirementThis position is classified as Remote within the United States.