Senior Power Management Engineer

Job Title: Senior Power Management Engineer Location: San Jose, CA (Onsite/Hybrid) – Remote from US locations considered Employment Type: Full-time About the Role We are looking for a highly skilled Senior Power Management Engineer to lead low power SoC design and architecture for next-generation AI accelerator chips. This role offers the opportunity to work across the full lifecycle of power intent definition, low power architecture, RTL design, verification, and silicon bring-up. You will collaborate with world-class teams in RTL, physical design, DV, firmware, and PMIC development to deliver cutting-edge low power solutions that optimize PPA (Performance, Power, Area). Key Responsibilities Define and implement low power SoC architecture, including DVFS, power gating, retention policies, and isolation strategies. Develop UPF/CPF power intent specifications, including power domains, level shifters, retention, and isolation flows. Design and validate power management units (PMU) for AI accelerator SoCs. Perform power modeling and analysis (leakage, dynamic power, DVFS schemes, thermal-aware sequencing). Partner with firmware teams to align on power sequencing, retention/restore logic, and PMIC interactions. Support low power verification using UPF-aware testbenches and static/dynamic signoff flows (VCLP, PTPX, PowerArtist, Calypto). Collaborate with silicon bring-up teams for post-silicon validation of power states, retention, and isolation logic. Drive flow automation and scripting (Python, Tcl, Perl, Shell) for power analysis and verification. Qualifications Must Have: Bachelor’s or Master’s in EE, CE, or related field. 5+ years of experience in SoC low power design/architecture with strong UPF/CPF knowledge. Proven expertise in multi-voltage domains, DVFS, power gating, isolation/retention cells. Strong RTL design skills (Verilog/SystemVerilog) and UPF-aware implementation experience. Familiarity with power analysis and verification tools (PowerArtist, PTPX, VCLP, CLP, Calypto). Proficiency in C/C++ (for firmware power sequence reviews, not development). Hands-on scripting skills (Python, Tcl, Perl, Shell). Job Type: Full-time Pay: $250,000.00 - $300,000.00 per year Benefits: 401(k) Dental insurance Health insurance Life insurance Paid time off Vision insurance Education: Bachelor's (Required) Experience: SoC low power design: 5 years (Required) multi-voltage domains: 4 years (Required) Verilog/SystemVerilog: 4 years (Required) scripting: 4 years (Required) Work Location: Remote