Staff Design Verification

Key Responsibilities Scroll down to find an indepth overview of this job, and what is expected of candidates Make an application by clicking on the Apply button. Develop and executeverification plansbased on design specifications Createtestbenchesusing SystemVerilog, UVM, or similar methodologies Writetest casesto validate functionality, performance, and corner cases Performfunctional and code coverage analysis Debug design issues and collaborate with design engineers to resolve bugs Use simulation tools (e.g., VCS, ModelSim, Xcelium) to run tests Develop reusable verification components and environments Conduct regression testing and ensure design stability Document verification results and provide detailed reports Required Skills & Qualifications Bachelor’s/Master’s degree inElectronics, Electrical Engineering, or related field Strong knowledge ofdigital design fundamentals Experience withHDL languages(Verilog/SystemVerilog) Familiarity withUVM (Universal Verification Methodology) Understanding ofsimulation and debugging tools Knowledge of scripting languages (Python, Perl, or Shell) Good xywuqvp problem-solving and analytical skills Preferred Skills Experience withASIC/SoC verification Knowledge offormal verification techniques Familiarity withprotocols(AXI, PCIe, USB, Ethernet, etc.) Exposure tocoverage-driven verification Experience with emulation or FPGA prototyping