<Back to Search
Signal and Power Integrity Engineer
Santa Clara, CAMarch 28th, 2026
We are now looking for a Signal & Power Integrity Engineer!NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle!What you'll be doing:Work on crafting creative Signal Integrity solutions to complex system design problems.Modeling and Optimization of vias, connectors, sockets, breakouts and various system components in 3D EM tools.System-level signal integrity simulations of high-speed NVlink 200Gbs+, USB-4, PCIe5, GDDR6, LP5X and other interfaces.Constant improvements of SI models using data from lab measurements and/or modelling tool/methodology updates.Substrate and board layout SI guidelines creation, review and post layout SI extractions.Simulation automation, data gathering, analysis and visualization using JMP, MATLAB or similar tools.Opportunity to work in a dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit.What we need to see:MS and/or PhD in Electrical and Computer Engineering (or equivalent experience) with minimum 2 years of work experienceStrong technical background in applied electromagnetics, waveguides, transmission line theory and signal processing will be highly valued.Familiarity with signal and power integrity concepts, design and analysis.Exposure to channel SI time domain simulations.Hands on use of 3-D modeling tools like ANSYS HFSS/Q3D, 2.5-D with ANSYS SIWAVE or similar and 2D such as Ansys2D.Familiarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro.Scripting skills for data post-processing, tool development and/or process automationWays to stand out from the crowd:Exposure to board/pkg technology & design.Understanding of circuit equalization techniques.Exposure to PDN evaluation using layout extraction tools for packages and PCBs and spice-based time domain simulations.Knowledge of programming language(s), especially PythonNVIDIA is widely considered one of the technology world’s most desirable employers. We employ some of the most forward-thinking and talented people in the world.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until March 21, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa Clara; US, TX, AustinType: Full time
Showing 800 of 29,799 matching similar jobs in Springbrook, ND
- Package Design Engineer
- Analog Design Engineer
- FPGA Engineer
- Senior Signal Integrity Engineer
- RF-mmWave IC Design / Packaging Engineer
- Principal IC Design Engineer - Analog
- Field-Programmable Gate Array. (FPGA) Engineer
- Senior FPGA Design Engineer
- Senior IP Design Engineer
- Verification & Validation (V&V) Engineer, Medical Devices
- Senior ASIC Design Engineer, Memory Controller
- Senior Analog IC Layout Design EngineerSaratoga, CAMarch 28th, 2026
- Electrical Engineer II - Effector Guidance Systems (3rd Shift)
- Senior Embedded Controls Engineer, Body Controls
- Avionics Engineering Lead
- Engineer Electronics 3
- Test Engineer, Maritime
- Formal Verification Engineer
- Wireless Design Verification Engineer
- Wireless Design Verification Engineer
- Cellular SOC Design Verification Engineer
- Touch HW EE Validation EngineerMillbrae, CAMarch 20th, 2026
- GPU Formal Design Verification Engineer
- SerDes Design and Validation Engineer
- Principal FPGA Design Engineer - Onsite Tucson, AZ
- Senior RF Sensor System Engineer
- Digital CCA Design
- Electrical Engineer
- Lead Avionics Responsible Engineer V, Flight Controls
- Electrical Engineer
- Electrical Engineer
- Traffic Signal Electronics Supervisor
- Operations Manager for EE Firm - Relocation available
- Physician / Family Practice / Oregon / Permanent / Family Medicine Physician with Security Clearance
- Sr. Field Tech - Power Systems Tech I, II, III, or IV
- Sr. Field Tech - Power Systems Tech II, III, or IV
- Power Systems Test Engineer - Relay Engineer
- Field Tech - Power Systems Tech I, II, III, or IV
- Manufacturing Engineer (Electrical/Systems)
- Instrumentation & Controls Engineer