DSP Design Engineer

Job Details:Job Description:About AlteraAltera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and software technologies that enable innovation across data centers, communications, automotive, aerospace & defense, and industrial markets. Our engineers tackle some of the most complex design challenges in the semiconductor industry, working at advanced technology nodes to build high-performance, power-efficient solutions used by customers worldwide.About the RoleThe DSP Design Engineer will oversee definition, design, verification, and documentation of state-of-the-art, AI-enhanced DSP IP for next generation FPGA families. Involves analyzing complex DSP topologies and develops parameterizable and efficient IP implementations. Will determine microarchitecture design, logic design, RTL coding, and system simulation. Performs all aspects of the design flow from high level design to synthesis. Oversees physical design place & route, and timing and power model generation. You will be participating in planning and execution of design verification and silicon validation. If you have strong DSP/arithmetic design background, and a passion for cutting-edge silicon development, the Silicon Design Engineering group would love to speak with you!ResponsibilitiesDesign and implement high-performance DSP IP for next-generation FPGAsContribute to all phases of the design lifecycle including specification development, RTL design, timing closure, power optimization, and design signoffDevelop and optimize high-speed arithmetic circuits with a focus on performance, power, and areaPerform datapath synthesis, static timing analysis (STA), and timing closure for advanced process technologiesCollaborate closely with architecture, verification, physical design, and software teams to ensure robust and scalable solutionsSupport formal verification, logic equivalence checking, and design validation activitiesParticipate in design reviews and provide technical leadership and mentorship within the teamSalary RangeThe pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$142,600 - $206,500 USDWe use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.Qualifications:Minimum QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 9+ years of hardware design experience on large, complex designs (or 4+ years with a PhD), including experience in one or more of the following areas:Proven experience in DSP and/or digital communication system datapath designSolid working knowledge of DSP and high-speed arithmetic circuit implementation, with a strong theoretical background in this domainIn-depth knowledge of datapath synthesis, static timing analysis, and timing closure techniques for high-speed designsHands-on experience with STA tools such as PrimeTime, particularly in advanced technology nodesExperience with formal verification and logic equivalence checkingStrong understanding of the full implementation flow including specification, design, timing closure, and power optimizationExperience with digital design flows including RTL simulation and timing constraintsFamiliarity with ASIC design flows, including libraries, EDA tools, and verification methodologiesWorking knowledge of tools such as PrimeTime, Design Compiler, and place-and-route (PnR) toolsPreferred Qualifications (Ways to Stand Out from the Crowd)Strong background in arithmetic operations - fixed point, floating point, and tensorJob Type:RegularShift:Shift 1 (United States of America)Primary Location:San Jose, California, United StatesAdditional Locations:Posting Statement: