Staff GPU Design Verification Engineer - Subsystems

Staff GPU Design Verification EngineerLeadStack Inc. is an award winning, one of the nation's fastest growing, certified minority owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.Location: Austin, TX (Onsite)Contract Duration: 6+ monthsPay Rate: $87–$108/hrMust-Have:Proven UVM (SystemVerilog) experience in design verification.Secondary Skills:Cache (L1/L2/LLC) or interface protocols (AXI/PCI).Key Responsibilities:Develop verification plans, coverage metrics, and sign-off criteria tied to specs.Build scalable UVM testbenches with SystemVerilog, C++, constrained-random, and assertion-based testing.Create targeted tests for subsystem interactions (blocks, interfaces, data paths).Debug failures, analyze root causes, and collaborate with design/architecture teams.Advance verification best practices and tools.Requirements:6+ years with BS (CS/Engineering); 4+ with MS; 2+ with PhD.Hands-on GPU/CPU/semiconductor verification.Computer architecture knowledge (block/subsystem integration).Strong C++/Python/Perl; UVM expertise (random testing, coverage, assertions).Debugging/problem-solving in fast-paced teams.Excellent communication for global collaboration.Nice-to-Have:Memory subsystems or coherent interconnects.Performance-aware verification/profiling.Hardware modeling/emulation.Passion for modern GPU architectures.