Lead Systems/DSP Engineer

Lead Systems/DSP EngineerEthernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company's breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.With talented employees on 4 continents, we have filed 50+ patents to date.Join Ethernovia's team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.Lead Systems/DSP EngineerSummary:We are seeking a seasoned DSP / System Architect to lead the design of next-generation high-speed (25G+) physical layer (PHY). In this role, you will define and drive the end-to-end DSP architecture, from system-level modeling through silicon validation, enabling highly optimized, low-power, and high-performance transceiver implementations.This is a high-impact technical leadership role at the intersection of signal processing, mixed-signal design, and system architecture. You will work closely with cross-functional teams to translate advanced algorithms into robust, production-ready silicon.Key ResponsibilitiesDefine and own the DSP/system architecture for high-speed transceivers, balancing power, performance, and silicon areaDrive key architectural decisions across DSP, analog front-end, and system partitioningLead system-level trade-offs and provide technical direction across the organizationDevelop and maintain high-fidelity system models of complete transceivers using MATLAB, Simulink, Python, and/or C++Design, evaluate, and optimize advanced equalization techniques, including FFE, DFE and MLSDArchitect robust Clock and Data Recovery (CDR) solutions with wide frequency acquisition range and very low phase noiseDevelop efficient and advance echo cancellation algorithms for full-duplex high-speed links optimizing for power and silicon areaDesign adaptive DSP algorithms with strong focus on rate of convergence, robustness, and implementation efficiencyDevelop channel model including nonlinear effects and complex noise sourcesTranslate system-level requirements into block-level specifications (AFE, ADC/DAC, PLL, DSP blocks, etc.)Collaborate closely with analog, RTL, and physical design teams to ensure accurate and efficient implementationEnsure alignment between algorithm models and hardware realizationDrive pre-silicon to post-silicon correlation, ensuring models accurately predict silicon behaviorDefine and support silicon bring-up, characterization, and debuggingEstablish lab validation methodologies and support compliance testing and performance benchmarkingContribute to system-level bring-up and production ramp readinessQualificationsMS or PhD in Electrical Engineering or a related discipline10+ years of experience in DSP/system architecture for high-speed communication systemsDeep expertise in digital communications theory including advanced, efficient and adaptive equalization and echo cancellation algorithms, CDR algorithms, phase noise characterization and loop dynamic analysis, channel modeling and nonlinear effectsStrong hands-on experience with system modeling tools (MATLAB, Simulink, Python, C++)Solid understanding of mixed-signal design fundamentals, including ADC/DAC architectures, PLL behavior and phase noise analysis, channel and analog front-end modeling including non-idealitiesProven track record of driving complex systems from concept to siliconExperience in designing high-speed IEEE 802.3 transceivers for automotive, robotics and data center applications over both optical and copper channelsPrior technical leadership or mentoring experienceWhat You Can Expect From Ethernovia:Technology depth and breadth expansion that can't be found in a large companyOpportunity to grow your career as the company growsPre IPO stock optionsCutting edge technologyWorld class teamCompetitive base salaryFlexible hoursMedical, dental and vision insurance for employeesSalary Range:The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $180,000 - $250,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.* Principals Only (No Agencies)#LI-Hybrid