Pre-Silicon Validation Engineer

Pre-Silicon Validation EngineerJob Location: Santa ClaraJob Type: Full-TimeExperience Required: 5+ YearsRole OverviewWe are seeking a highly skilled Pre-Silicon Validation Engineer with strong expertise in DFT implementation, verification, and ATPG methodologies for advanced semiconductor/SoC platforms. The ideal candidate will have hands-on experience in Scan, MBIST, IJTAG, and DFT verification activities along with exposure to industry-standard DFT tool suites.Key ResponsibilitiesPerform DFT insertion and validation for SCAN, SSN, and MBIST Repair implementation.Generate DFT collaterals required for Test Timing, Place & Route, and manufacturing test flows.Work on verification of DFT features including:Boundary ScanJTAGSCANMBISTHigh-Speed IO interfacesAnalyze and debug ATPG DRC issues and improve test coverage metrics.Generate ATPG patterns for multiple fault models.Understand and implement IJTAG (IEEE 1687) standards including ICL and PDL specifications.Collaborate with RTL, Physical Design, and Validation teams for seamless DFT integration.Support silicon bring-up and pre-silicon validation activities.Required SkillsStrong experience in:DFT InsertionSCAN with SSNMBIST Repair Implementation & VerificationATPG Flow & Coverage AnalysisGood understanding of:IEEE 1687 / IJTAG standardsICL and PDL specificationsBoundary Scan and JTAG architecturesHands-on experience with DFT tools such as:Synopsys DFTMAXMentor TessentSiemens DFT Tool SuiteExperience in debugging ATPG DRC violations and pattern generation.Familiarity with semiconductor validation and SoC design flows.Preferred QualificationsExperience working on high-performance SoC/ASIC platforms.Strong debugging and scripting skills.Excellent communication and collaboration abilities.EducationBachelor’s or Master’s degree in Electronics, VLSI, Electrical Engineering, or related field.