SerDes Circuit Design Engineer

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple's world-leading system-on-chip (SOC).In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create, execute and drivestate-of-the-art IPs key to Apple's products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.If you have strong fundamentals and a track record of tackling technical challenges,If you are passionate about learning new skills and improving the value of your work,If you like to be tuned to the big picture while diving deeply into the details to innovate and tackle problems.We invite you to join and grow with our team!You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best-in-class power, performance, and area (PPA).You will be leading discussions with cross-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications, mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs, on regular basis you will interact with your peers/management to communicate progress, discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.Deep understanding of analog mixed-signal design with experience in high-speed serial links.Experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, FiltersUnderstanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniquesUnderstanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops)Proven track record of working with system and architecture teams to drive block-level and IP requirements for high-speed IO in 100+ Gbps NRZ and PAM applicationsProven track record of working with large teams and guiding junior engineers to develop circuit components required in TX, RX, PLL etc. of a high-speed IO.Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.) with solid understanding of digital design conceptsExperience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE, DFE, de-emphasis) for 100+ Gbps NRZ and PAM applicationsExperience with EQ adaptation methods and circuit implementations to improve PPASolid understanding of CDR architectures and implementationsExperience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog, Matlab, Python, VerilogAMS)Hands-on experience to drive lab testing, debug and data analysisHands-on experience in advanced CMOS technologies, design with FinFet technologyHands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterizationConcepts of timing closure and related industry tools (e.g., Nanotime, Primetime)Concepts of IP delivery and quality checksKnowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desiredSkills in scripting and automation to enhance efficiency are highly desirableArray