STA Engineer

Job Description: ◦ Experience with Integration for STA: including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction. ◦ Timing closure with various timing ECO including transition, setup, hold, noise, crosstalk, and power recovery. ◦ Familiarity with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates ◦ Synthesis Tools: Synopsys DC/DCG/FC. ◦ Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus. ◦ Scripting: TCL, Perl, or Python.