ASIC Design Verification Engineer, Machine Learning

Overview As an ASIC Design Verification Engineer, you will verify complex digital designs and shape TPU architecture within AI/ML hardware. You’ll develop and refine constrained-random verification environments using SystemVerilog and UVM, or formal methods, to exercise designs and uncover bugs. You will own the full verification lifecycle from planning to coverage closure, collaborating with design teams to deliver functionally correct blocks for tape-out. This role supports Google’s AI infrastructure at scale, contributing to high-impact silicon solutions powering global services. Your work directly influences the performance and reliability of TPU-based AI/ML workloads. Compensation / Benefitsbonus targetequitybenefits ResponsibilitiesVerify complex digital designs and identify verification scenarios through collaboration with design engineersCreate and enhance constrained-random verification environments using SystemVerilog and UVM, or perform formal verification with SVADevelop and write coverage for stimulus and corner-cases; monitor and close coverage gapsDebug tests with design engineers to ensure functional correctness of blocksManage the full verification lifecycle from planning to test execution and coverage analysisCollaborate with cross-functional teams on TPU architecture integration within AI/ML systems Key requirementsBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field4 years of experience with design verificationExperience with SystemVerilog/Verilogproblem-solvingstrong communicationcollaborationSystemVerilog/Verilogconstrained-random verification (CRV)UVM