Physical Design Engineer

Job Title: Physical Design Engineer Location: Austin, TX And Atlanta. GANumber of Positions: 10 LocationDomain: VLSI / Semiconductor / ASIC Physical DesignJob Summary :We are seeking an experienced Physical Design Engineer with 5–10+ years of hands-on experience in ASIC physical design. The candidate will be responsible for end-to-end block/full-chip physical design activities from RTL2GDSII/Netlist2GDSII, ensuring high quality, STA, SI, EMIR and PV (DRC/LVS/ERC/ANT)-clean layouts.Key ResponsibilitiesDrive full-chip SoC/Block level physical design from RTL2GDSII/Netlist2GDSII Perform top-level/sub-system/Block synthesis, floorplanning, partitioning, and hierarchical integrationDevelop and implement full-chip/Block level power planning and power grid strategies Manage block integration, timing budgeting, and interface closure Execute and optimize placement, CTS, routing, and post-route flows at full-chip levelLead full-chip timing closure across MMMC scenariosHandle top-level congestion, SI, noise, IR drop, and EM closurePerform and drive physical verification closure (DRC/LVS/ERC/ANTENNA)Manage ECO flows including full-chip and block-level ECOs Collaborate closely with RTL, synthesis, STA, DFT, packaging, and verification teamsSupport tapeout planning, signoA checks, and final delivery milestonesBuild and enhance automation scripts and PD flowsRequired Technical SkillsStrong experience in full-chip SoC implementationDeep expertise in:Top-level floorplanning and partitioningChip-level power planning and multi-voltage domainsHierarchical and flat implementation flowsTiming budgeting and interface timing closureCTS and clock architecture at SoC level o Congestion and routing optimizationStrong knowledge of:MMMC timing setup and closureOCV/AOCV/POCV, SI and Crosstalk analysisMulti-voltage and low-power flows (UPF/CPF)IR/EM and thermal considerationsHands-on experience with tools such as:Cadence Innovus / Synopsys ICC2 PrimeTime / TempusVoltus / RedHawkCalibre / PegasusPreferred QualificationsExperience in advanced nodes (≤16nm / 7nm / 5nm preferred)Exposure to large SoC designs with multiple clock and power domainsExperience handling high-speed interfaces and hard macrosKnowledge of packaging interactions and bump/IO planningStrong Tcl scripting skills; Python/Shell scripting is a plusExperience mentoring engineers and leading PD closure tasks Soft SkillsStrong debugging and problem-solving skillsAbility to work independently and drive closureGood communication and cross-team collaboration skillsExperience mentoring junior engineers (preferred for senior candidates)EducationB.E./B.Tech/M.E./M.Tech in Electronics / VLSI / Electrical Engineering or related f ield