Design Verification Engineer -Performance Modelling

Role: Design Verification Engineer -Performance Modelling Location: Sunnyvale CA or Austin, TX Duration: Full Time Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regression runs, analyze results, and contribute to continuous improvementsIntegrate and run power-aware simulations, low power checks, and work with UPF/CPF as neededCollaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domainsDocument test environments, testplans, and results for internal and external reviews.