RTL engineer only W2
Knowledge of memory controller u-architecture. – current experience 3-5 years.
Familiarity with different memory technologies like LPDDR4/5, HBM.
Knowledge of JEDEC memory standards preferred.
Knowledge of AES, ECC, RAS features preferred.
RTL Design Skills is a must – current experience
Job Type: Full-time
Schedule:
Monday to Friday
Experience:
memory controller u-architecture: 4 years (Preferred)
LPDDR4/5, HBM: 3 years (Preferred)
RTL Design: 2 years (Preferred)
Ability to Commute:
Austin, TX (Preferred)
Work Location: In person