Principal DFT Engineer

A company is looking for a Principal DFT Engineer. Key Responsibilities: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan, and MBIST Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers Oversee scan insertion, ATPG, and Memory/Logic BIST while collaborating with cross-functional teams to ensure high test coverage Required Qualifications: 10+ years of experience in DFT, with at least 2 years in a leadership or principal role Mastery of industry-standard tools such as Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Genus/Modus Deep expertise in MBIST, SCAN, IJTAG, and boundary scan Proven track record with FinFET nodes (7nm, 5nm, or below) Experience managing DFT in multi-voltage/power-gated designs