Design Verification Engineer Intern

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Design Verification Engineer InternCadence Silicon Realization Group is hiring students to join our services teams in San Jose. This is an amazing opportunity to work as an engineering intern at a world leader in computational software, semiconductor design IP, and system verification hardware. Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.We are seeking a motivated Design Verification Engineer Intern to join our Silicon Realization Group (SRG). In this role, you will work closely with Verification engineers to verify digital designs for correctness, performance, and functionality. You will develop and execute verification testbenches, debug simulation failures, and contribute to high-quality silicon delivery.Key ResponsibilitiesDevelop and maintain verification environments using SystemVerilog/UVMWrite and execute test cases to validate RTL functionalityDebug design and verification issues using simulation and waveform analysisCollaborate with design teams to review specifications and verification plansQualificationsCurrently pursuing a BS/MS in Electrical Engineering, Computer Engineering, or related fieldStrong understanding of digital design fundamentals and RTL conceptsWorking knowledge of Verilog/SystemVerilog; UVM is a plusFamiliarity with EDA simulation tools and scripting (Python/Perl preferred)Good analytical, communication, and teamwork skillsWe’re doing work that matters. Help us solve what others can’t.