Senior Hardware Engineer – Signal Delivery

Senior Hardware Engineer – Signal Delivery (Signal Integrity, PCIe, UCIe) owning end‑to‑end physical signal delivery across semiconductor test systems, combining 3D EM simulation and hands‑on lab validation in North Reading, MA. We’re hiring a Senior Hardware Engineer to join our client’s small, highly experienced on‑site engineering team in North Reading, Massachusetts. This role supports advanced R&D for semiconductor test systems and requires immediate, senior‑level contribution. This is not a ramp‑up or training role and is intended only for engineers with proven, end‑to‑end ownership of signal delivery challenges in real hardware systems. This position focuses specifically on system‑level signal delivery, meaning the engineer owns how electrical signals are preserved across the entire physical path from the device under test through probing interfaces and into test instrumentation. Success in this role requires deep understanding of how signals behave across physical distance, interfaces, and transitions under real operating conditions. This is a design‑and‑lab execution role. The engineer will design solutions, analyze them using 3D electromagnetic simulation, and then spend significant time building, testing, and iterating hardware in the lab. Candidates whose experience is limited to analysis, modeling, or narrowly defined components will not be a fit.Core ResponsibilitiesOwn end‑to‑end signal‑delivery architecture, from DUT through probing, interconnects, and test instrumentationDesign, simulate, prototype, and validate high‑speed signal‑delivery solutions for semiconductor test systemsApply 3D electromagnetic simulation to analyze and resolve signal integrity challenges across complex interconnect pathsSupport PCIe‑based systems, with strong preference for UCIe (next‑generation interconnect architecture)Translate simulation results into physical lab builds, measurements, and iterative design improvementsPerform signal integrity validation using oscilloscopes, TDR, and VNA equipmentCollaborate closely with PCB, packaging, mechanical, and system‑level teams to optimize signal performanceSupport product development from concept through implementation, ensuring robust signal integrity and reliabilityPresent clear, data‑driven technical findings, risks, and tradeoffs to engineering leadershipRequired Qualifications (Non‑Negotiable)Bachelor’s or Master’s degree in Electrical Engineering or related disciplineSenior‑level experience owning signal delivery problems across complete physical pathsHands‑on 3D electromagnetic simulation experience requiredHFSS strongly preferred; candidates without real 3D EM analysis experience should not applyPractical experience supporting PCIe‑based systemsFamiliarity with UCIe is a strong advantageDemonstrated ability to connect simulation, lab measurement, and hardware iterationProven ability to work productively in lab‑intensive environmentsClear understanding of how signals degrade, couple, and distort across real hardwareWho This Role Is Intended ForThis role is best suited for:Senior Hardware Engineers – Signal IntegritySignal Integrity EngineersHigh‑Speed Hardware ArchitectsEngineers with system‑level interconnect, connectivity, or signal‑delivery expertiseEngineers who are comfortable discussing complete signal paths, physical impairments, protocol behavior at the channel level, and lab‑verified outcomes will be the strongest fit.On‑Site RequirementsMinimum 4 days per week on‑site in North Reading, MassachusettsHands‑on, lab‑driven engineering environmentOnly candidates within commuting distance will be consideredNo relocation availableBenefitsThe client offers a comprehensive benefits package, including medical, dental, and vision coverage, retirement savings plans, paid time off and holidays, tuition assistance, and additional wellness programs.ApplyQualified candidates who meet the senior‑level technical requirements and on‑site expectations are encouraged to apply for confidential consideration.