Technical Specialist - Silicon Platform Validation, Python

Technical Specialist - Silicon Platform Validation, PythonWe are looking for a Silicon Interposer Design Engineer to drive the physical design, layout, and technology development of silicon interposers used in next-generation 2.5D and 3D heterogeneous integration platforms. You will own the interposer design from architecture definition through tapeout, working at the intersection of semiconductor process technology, package integration, and system-level performance optimization.Key Responsibilities:Lead the physical design and layout of silicon interposers for multi-chiplet integration (compute, HBM, I/O, networking dies)Define interposer architecture including die placement, bump map assignment, RDL routing strategy, TSV farm layout, and power/ground distributionDevelop and optimize RDL (Redistribution Layer) routing for high-density die-to-die interconnects, ensuring compliance with electrical, thermal, and mechanical constraintsDesign TSV (Through-Silicon Via) arrays and transitions — including TSV placement, keep-out zones, stress-aware floorplanning, and landing pad optimizationCollaborate with SI/PI engineers to meet signal integrity and power delivery targets across the interposerDefine and validate interposer stackup (metal layers, dielectric thickness, TSV dimensions) in coordination with foundry process capabilitiesPerform DRC/LVS verification and ensure design compliance with foundry design rules (TSMC CoWoS, UMC, GlobalFoundries, etc.)Work with EDA tool flows for interposer-specific design (custom routing, via pillar arrays, micro-bump pitch optimization)Co-optimize interposer design with package substrate and PCB teams for seamless chip-package-board integrationSupport thermal-mechanical analysis by providing accurate layout data for warpage, stress, and reliability simulationsInterface with foundry partners for technology selection, design rule clarification, and tapeout executionDrive DFM/DFT strategies to improve yield and testability of interposer-based productsSupport silicon bring-up, debug, and failure analysis of interposer-related issuesSkill Requirements:5+ years of experience in silicon interposer design, advanced packaging physical design, or semiconductor back-end-of-line (BEOL) designStrong proficiency with physical design and layout tools: Layout & Routing: Cadence Virtuoso, Cadence APD (Advanced Package Designer), Synopsys IC Compiler II, Siemens Calibre Verification: Cadence PVS, Mentor Calibre (DRC/LVS/ERC) Parasitic Extraction: StarRC, QRC, Calibre xRCDeep understanding of silicon interposer process technology: RDL metallization (Cu damascene, semi-additive process) TSV fabrication (via-first, via-middle, via-last) Micro-bump and C4 bump technology Wafer thinning and backside processing