Senior ASIC/FPGA Verification Engineer - SystemVerilog/UVM

A technology solutions company in California is seeking a Verification Engineer to write SystemVerilog/UVM testbenches for ASICs and FPGAs. The ideal candidate will have a Bachelor's degree in a related field and experience with ASIC/FPGA verification. Familiarity with scripting in Python or Perl is essential. You will develop reusable UVM components and run various simulations. The position requires collaboration with hardware teams and offers opportunities for growth and skill enhancement. J-18808-Ljbffr