Senior DFT Engineer Post-Silicon Yield & Debug

Broadcom Inc. is seeking a DFT Engineer for the Core Switching Group at our R&D center in San Jose, CA. You will lead DFT ATPG/MBIST pattern development, debug, and drive yield improvements across wafer sort and final test, working with cross-functional teams and leveraging data analytics to build proactive yield models. The role demands deep CMOS physics knowledge, experience with Tessent, and strong scripting for automation; a Bachelor's degree with 8+ years (or a Master’s with 6+ years) is #J-18808-Ljbffr