<Back to Search
Custom Logic Design & STA Engineer
Cupertino, CAMarch 28th, 2026
**Role Number:** 200626480-0836**Summary**Imagine what you could do here at Apple! Together we could help craft the next generation of the world's finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. The Analog/Mixed Signal Design team is searching for a self-motivating engineer for the role of Custom Logic Design and STA engineer.As a member of the team, we will be working on the leading-edge technology to build best-in-class custom mixed-signal designs used to connect our world-class products to the world as well as optimizing their performance. You will become part of a development team that cultivates engineering excellence, creativity, and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in this type of environment. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products?**Description**In this role, you will perform timing analysis on custom design circuits, delivery timing views to integration teams, as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers, and cross-functional teams at the silicon and module levels.**Minimum Qualifications**+ BS and a minimum of 10 years relevant industry experience.+ Solid understanding of timing analysis concepts such as setup/hold time calculation, POCV on timing paths, timing constraints, transistor-level delay characterization, and rise/fall time balancing.+ Experience of timing analysis and verification in high-speed design such as SerDes and ADC.+ In-depth knowledge and analytical understanding of mixed-signal design techniques.+ Strong track record of delivering silicon IPs with design and verification.+ Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.**Preferred Qualifications**+ Experience with STA tools such as NanoTime, PrimeTime, and Tempus.+ Experience in analog/mixed-signal circuit design from architecture to fundamental implementation.+ Experience in SRAM design.+ Experience in timing / SDC constraints generation and management.+ Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with OCV / AOCVM / POCV.+ Proficiency in scripting languages (Python, Tcl and Perl).+ Familiarity with synthesis, logic equivalence, DFT, and backend related methodologies and tools.+ Strong communication and interpersonal skills.Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (https://www.eeoc.gov/sites/default/files/2023-06/22-088\_EEOC\_KnowYourRights6.12ScreenRdr.pdf) .
Showing 100 of 10,615 matching similar jobs in Springbrook, ND
- Hardware Digital Design Engineer
- Hardware Digital Design Engineer
- Wireless Design Verification Engineer
- SerDes Design and Validation Engineer
- ASIC/FPGA Design Engineer (SMES)
- Ride Control Hardware Engineer, Principal (ControlsAutomation)
- Principal RF Design Engineer
- Senior RF/Mixed-Signal IC Design Engineer
- Asic/Fpga Design Engineer
- ASIC/FPGA Design Engineer (SMES)
- Senior IC Design Engineer: IO SI & PD + Equity
- Senior IC Design Engineer: IO, SI & PD Expert
- Sr. Microarchitect & RTL Design Engineer
- Mixed Signal Design Engineer
- Mixed Signal Design Engineer
- Lead Systems Engineer
- Design for Test Engineer (Temporary Contract Staff Augmentation Role)
- Intern- Intergrated Product Services Design 1
- Senior FPGA Engineer, LEO Payload FPGA, Amazon Leo Hardware Development
- Engineer, Senior
- Principal Mixed-Signal/Analog Design Engineer
- Mixed-Signal IC Design Engineer
- Analog Mixed Signal IP Engineer
- GNSS Validation Engineer
- Hardware Systems Signal Integrity Engineer - iPhone
- RFIC Design Engineer
- Circuit Design Engineer - Library
- RFIC Design Engineer
- ASIC Design Engineer
- Wireless SoC RF Integration and Validation Engineer
- PLL Design Engineer
- IC Package Design Engineer
- Analog Architect
- SerDes Circuit Design Engineer
- Intern, RFIC Design Validation and Characterization - Summer 2026
- SerDes System Validation Engineer
- Experienced Analog/Mixed Signal IC Design Engineer
- FPGA Design - Lead Research Engineer "CLEARANCE REQUIRED"
- Lead Electrical Design Engineer
- FPGA Design Engineer