Lead 2.5D/3D IC Package Layout Engineer

Annapurna Labs (U.S.) Inc. in Cupertino seeks a Sr. Package Layout Engineer to own end-to-end physical design of advanced IC packages for next‑gen ML and data center ASICs. You will oversee the package layout from floor planning through tape‑out, coordinating with silicon, SI/PI, and manufacturing teams to meet performance and reliability targets. You will define floorplans, drive RDL/substrate routing, and ensure design-for-manufacturing alignment with OSAT partners, while mentoring junior #J-18808-Ljbffr