SoC DV Engineer

8-12 years of experience in SoC Verification with strong proficiency in:Verilog-HDLC test development at SoC levelSV AssertionsTCL/Python/Shell scriptingExperience with:Protocol Knowledge (JTAG, SPI, UART, serial communication protocols and AMBA APB, AHB interconnect protocols)Gate-level simulation & SDF flowsCoverage tools and methodologies (functional + code coverage)Hands-on experience debugging complex SoC issues involving ARM subsystems.Preferred QualificationsPrior work on mixed-signal or digital-analog interface verification.Understanding of AHB/APB/AXI interconnects.Exposure to version control like GitHub Actions, Jenkins, or similar.