IC design engineer

IC Design EngineerLocation: Sunnyvale, CA or Austin TX with some remote capabilityResponsibilities:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause, and resolve functional failures in the design, partnering with the Design teamCollaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design qualityMinimum Qualifications:B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer ScienceHands-on experience in Verilog, System Verilog, C/C++ based verification, and UVM methodologyExperience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologiesExperience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cyclePreferred Qualifications:Experience in the development of UVM based verification environments from scratchExperience with Design verification of Data-center applications like Video, AI/ML, and Networking designsExperience with revision control systems like Mercurial(Hg), Git or SVNExperience with verification of ARM/RISC-V based sub-systems or SoCs