Yield Engineer: Defect Reduction & Process Optimization

Tower Semiconductor Ltd. is seeking an experienced engineer to sustain defectivity monitoring and improve wafer yields across 0.35–0.13um RFCMOS/SiGe BiCMOS processes. You'll partner with Integration, Process, Equipment and R&D to meet performance, quality, and cycle-time goals. You will analyze defect trends, investigate particulate contamination sources, and drive corrective actions with global teams to optimize fabrication efficiency and product quality.