Digital Engineer VHDL FPGA

Digital Engineer VHDL \ FPGA - 2 positions MUST BE A US CITIZEN Willing to obtain a security clearance WORK SHIFT: 1st Shift (9/80A) • Possible hybrid or remote for applicants with exceptional experience. Description Digital Engineer - San Diego, CA. Responsibilities: • Design, develop, integrate and test VHDL-based digital designs for our end-user customers and businesses, primarily focused on software defined radio VHDL firmware code bases. • Work using FPGA programming development tools and environments • Work with multi-disciplinary teams, such as with Systems Engineering, Digital Engineering, Hardware, and Integration & Test • Work in waterfall or Agile software development environment • Analyze system concept of operation, requirements and design documents to resolve functional, performance or timing issues. Basic Qualifications for Digital Engineer: • BS + 5 years of experience in related STEM field; MS + 3 years of experience. • Significant hands-on current experience in the field of VHDL design. • Candidate must have excellent written and communication skills and be able to work independently and within groups. • Candidate must have working knowledge of formal engineering development process, VHDL design and verification. Preferred Qualifications for Digital Engineer: • 8 or more years of professional technical experience. • Experience with VHDL design and OSVVM verification for FPGA firmware • Experience with AMD/Xilinx series including Zynq, Kintex, Ultrascale, Versal family of devices. • Experience with Communication Protocols (I2C, SPI, UART, PCIe, Ethernet) • Experience with Electronic Design Automation (EDA) tools: Vivado, Quartus, QuestaSim • Knowledgeable in FPGA physical constraints and achieving timing closure. • Generation of Test benches and support of formal VHDL Verification. • Experience with board RO system level debug using test equipment such as oscilloscopes and logic analyzers. • Experience with translating systems requirements into programmable logic requirements, design documents, and test specifications. • Candidate should have hands on experience with DoD communications systems. Intake Questionnaire Details from the manager: • FPGA VHDL design primarily using AMD/Xilinx FPGAs and supporting tools and/or formal verification using the OSVVM framework • Typical group size is team of 4-8 engineers • AMD/Xilinx SoC using Versal or Vivado, Siemens QuestaSim, OSVVM for formal verification • The team is collaborative and filled with engineers from multiple levels. Project goals and expectations are clearly defined. The team is extremely collaborative, making it easy to ask questions. Designers and verifiers work together as a team to understand requirements and close out issues promptly. • The typical day depends on where the program is at in the design phase. It could vary from writing requirements, coding the module, debugging a simulation, or in the lab. There will also be time spent working with fellow team members working to solve a problem together. Status meetings are typically held once a week with the entire design and verification team. • The training process is coming up to speed with the four VHDL engineering processing directives and how to apply them to your role. There is one for defining requirements, designing to the requirements, verifying the requirements, and finally generating a build. VHDL designers should expect to take advanced Vivado trainings, and verifiers should expect to take advanced OSVVM trainings.