DFT Engineer

DFT EngineerLocation: San Jose, CA, Fort Collins, CO, Allentown, PA, Irvine, CA, Minneapolis, MN. Duration: Full-time/PermClient's ASIC Product Division is seeking candidates for a DFT Lead position at our Fort Collins, Colorado Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would be required to work on various phases of SoC DFT related activities for Client's APD (ASIC Products Division)'s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. It is expected that you can code usingTCL, PERL, RUBY, PYTHON, C++ or similar.Responsibilities:Understanding client & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASICImplementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integrationWorking closely with STA and DI Engineers design closure for testGenerating, Verifying & Debugging Test vectors before tape release.Validating & Debugging Test vectors on ATE during the silicon bring up phaseAssisting with silicon failure analysis, diagnostics & yield improvement effortsInterfacing with the customer, physical design and test engineering/manufacturing teams located globallyWorking closely with I/P DFT engineers & other stakeholdersDebugging customer returned parts on the ATEInnovating newer DFT solutions to solve testability problems in 7nm & beyondAutomating DFT & Test Vector Generation flowsSkills/Experience:Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)Logic BIST design and debug experienceWell-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan)Experience in Verilog coding, testbench generation & simulationMemory BIST insertion and verification experience (SRAM, CAM, eDRAM)The ability to work in a multi-disciplined, cross-department environmentSolid knowledge in analog and digital circuit design, and device physics fundamentalsGood understanding of Si processing, logical and physical synthesis, and transistor reliability principlesExcellent problem solving, debug, root cause analysis and communication skillsExperience working on ATE is a plusEducation & Experience:Bachelors in Electrical/Electronic/Computer Engineering, 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering, 10+ years of relevant industry experience