DRC/LVS Engineer

IBMFG2JP00036309 --DRC/LVS EngineerRemote work is AllowedUS Citizen Required DRC/LVS EngineerRole OverviewWe seek experienced LVS/DRC engineers to develop high-quality verification decks for our PDK. This contractor position focuses on translating design rules, ground rules, and design manual specifications into robust, coded verification decks. We are looking for seasoned professionals who can take ownership of rule implementation across multiple technologies and process nodes.The OpportunityOur current DRC/LVS bandwidth is constrained. Today, a single experienced developer manages multiple technologies, multiple decks, and complex rule sets across our PDK portfolio. We need additional engineering capacity to:Develop and optimize DRC decks that translate design rules and ground rules into verification codeAuthor LVS decks to ensure layout-to-schematic accuracy and connectivity verificationSupport multiple technology nodes and design kit flavors simultaneouslyWork with design manuals and process specifications to code complex hierarchical and multi-layer rulesValidate deck quality through rigorous testing and sign-offThis is core PDK development work. We value experienced engineers who can work independently and deliver high-quality verification decks that designers rely on.Required Experience5+ years of professional DRC and/or LVS deck developmentProven expertise in translating design manuals and ground rules into verification codeStrong proficiency in PxL (Synopsys) and/or SVRF (Calibre)Hands-on experience developing decks across multiple technologies or process nodesUnderstanding of hierarchical rule structures, multi-layer verification, and deck validation methodologyExperience working with EDA tools in professional settings; comfort with scripting and automationPrimary Tools & EnvironmentSynopsys ICValidator (primary tool for our DRC development)Cadence Virtuoso (design and verification platform)OPTIONAL: KLayout (for rule checking and mask data analysis)Required LanguagesPxL (Synopsys) – preferred for our primary developmentPython – for scripting, automation, and deck generationOPTIONAL: SVRF (Calibre) – for multi-tool verification and rule translation Preferred QualificationsExperience with SKILL (Cadence) for rule integration and automationProficiency in Siemens (Mentor) Calibre rule developmentExperience developing LVS decks or familiarity with LVS verification methodologiesBackground in advanced technology nodes (FinFET, nanosheet, or below)Experience with PDK delivery, design rule documentation, and deck sign-off processesTrack record of delivering high-quality verification decks that passed design reviews and tapeoutsWhat You'll DeliverHigh-quality DRC decks that accurately encode design rules and ground rulesLVS decks (as applicable) for device and connectivity verification across process nodesWell-structured, maintainable verification code in PxL and/or SVRFComprehensive deck documentation and validation reportsSupport for multiple technologies and design kit versionsThis is an opportunity to contribute directly to PDK quality and join a team building next-generation semiconductor design infrastructure. We welcome candidates with proven expertise and a commitment to precision in design verification.